Candorwise

ASIC RTL Design Engineer

Category: Engineering

Experience:5–15 years
Location:Hyderabad, Bengaluru

Your team

Join a team working on ASIC RTL design and SoC/IP integration, collaborating across design, verification, physical design, DFT and software teams to develop high-quality semiconductor solutions.

Your job

  • Design and integrate ASIC RTL, IPs and SoC subsystems using Verilog/System Verilog.
  • Perform RTL quality checks including Lint and CDC.
  • Work with AMBA protocols and interfaces such as PCIe, DDR and Ethernet.
  • Use tools like SpyGlass, Synopsys DC, Verdi and Xcelium for design and debugging.

Capabilities

  • Strong ASIC RTL design and SoC/IP integration skills.
  • Good knowledge of Verilog/SystemVerilog and AMBA protocols.
  • Experience with Lint, CDC, synthesis and RTL quality checks.

Qualifications

Bachelor’s/Master’s degree in Electronics, Electrical Engineering, VLSI or related field.